1. Field of the Invention
The invention relates to buffer storage technology, more particularly to an adaptive buffer device and a method thereof.
2. Description of the Related Art
Referring to FIG. 1, in a conventional circuit design, a processor 7 writes computational data to an external memory 8. However, since the processor 7 generally operates at a speed far higher than that of the memory 8, a built-in buffer device 71 is often used to store the computational data temporarily without stalling the processor, so as to prevent a reduction in efficiency due to constraints attributed to the memory 8.
When a conventional buffer device receives from the processor 7 a plurality of adjacent items of data (data width equals to a word) and corresponding addresses, the data and the addresses will be recorded respectively in a plurality of data entries each having a storage width of one word and a plurality of address entries. If the buffer device supports write merge, when the corresponding addresses of a part of the adjacent items of data are ascendingly consecutive, they can be merged into a burst write command for a system bus 9 to serve as a basis for transmission of that part of the adjacent items of data. Although such a method does not require transmission of the addresses of all the data one by one and hence can reduce the amount of data to be sent via the system bus 9, since the storage width of each data entry can contain only one item of data, write merge is possible only when the addresses of the adjacent items of data are ascendingly consecutive. Thus, the probability of performing write merge is low.
Another conventional buffer device expands the storage width of each data entry to four words. Before the buffer device is made full by writing, data with consecutive addresses can be recorded in the same data entry. Therefore, even if the data with consecutive addresses are not written to the buffer device in sequence, there are chances that they may still be merged. However, in situations where the addresses of several adjacent items of data are not consecutive, it is possible that a data entry only records an item of data, thereby resulting in considerable waste of storage space.
In addition, there is prior art in which an entry can be configured to record either an address or data, which is different from the aforementioned conventional buffer devices which require preparation of address entries and data entries. When a previous address and a current address are ascendingly consecutive, it is only necessary to record the corresponding current data, and there is no need to record the current address. Moreover, the current data can be merged with the corresponding previous data into a burst write command. However, it the addresses are not ascendingly consecutive, both the address and the data need to be recorded. Since only adjacent items of data can be merged, it is still difficult to reduce the amount of data for the system bus 9.